Marvell’s second-generation Structera X 3406 and 3506 are CXL 3.2 memory-expansion controllers with six DDR4 or DDR5 channels, 50% more than the previous generation. The company says the 3406 supports up to 9 TB of DDR4 across 18 RDIMM slots, while the 3506 supports up to 6 TB of DDR5 across 12 slots in its October 12 announcement.
The new controllers also support memory sharing with up to four hosts and up to 256 GB/s of host bandwidth over PCIe 6.0 x16, according to Marvell. That gives infrastructure teams a per-controller capacity target, rather than another accelerator compute number.
Marvell says inline LZ4 compression can reach 250 GB/s and provide two to three times more effective capacity, depending on workload. It also reports 40% to 50% faster time to first token at the same context length, or up to twice the supportable context window at the same latency, compared with the first generation. The capacity limits are product specifications; the inference-speed figures are Marvell’s comparison with its earlier generation, not independent benchmark results.
The 3406 and 3506 are being demonstrated at the OCP Global Summit, and Marvell expects them to begin sampling in the first quarter of 2027. That is a sample window, not a public ship date. The company says its first-generation 2404 and 2504 controllers are already shipping to hyperscalers.
Neon Control’s memory-bandwidth explainer covers the related challenge of moving data to AI compute. Marvell’s new controllers address memory capacity and bandwidth together, while its inference gains remain company-reported comparisons.
