Vayavya Labs says it has built SystemC/TLM virtual platforms for Tenstorrent security and system-management IP since 2024. In an Oct. 8 announcement, the companies describe models that let software and validation teams develop, test, and debug against virtual hardware before physical silicon is ready.
The modeled blocks include security enclave processor registers, system management controller logic, DMA engines with secure zeroing, boot and fuse infrastructure, and a hardware security module for cryptographic operations. Vayavya says its latest delivery was a phased release of Tenstorrent’s Open Chiplet Harness SEP virtual platform on two independent simulation targets, with added system management controller and harness capabilities.
The models use Vayavya’s CSML SystemC library and TvastaaVP platform. That puts the work at the pre-silicon testing stage. Our report on Microsoft’s AI-assisted RISC-V design project covers a different step in chip development: generating and refining processor logic rather than testing security and management blocks.
